Assignment 3 CMSC611 – Advanced Computer Architecture, Fall 2019 1/1 University of Maryland Baltimore County Department of Computer Science and Electrical Engineering CMSC 611 – Advanced Computer Architecture Assignment #3 Due: Thursday 10/17/2019 in class Question 1: (100 Points) The goal of this exercise is to compare how a loop runs on a variety of pipelined versions of MIPS. The loop implements the vector operation Y = a × X + Y. Here is the MIPS code for the loop: foo: L.D F2, 0(R1) ; Load X(i) MULT.D F4, F2, F0 ; multiply a * X(i) L.D F6, 0(R2) ; load Y(i) ADD.D F6, F4, F6 ; add a * X(i) + Y(i) S.D 0(R2), F6 ; store Y(i) ADDIU R1, R1, #8 ; increment X index ADDIU R2, R2, #8 ; increment Y index SLTIU R3, R1, done ; test if done BEQZ R3, foo ; loop if not done The conditional branches are resolved in the ID stage. Use the FP latencies shown in the following table but assume that the FP unit is fully pipelined: Functional unit Latency Integer ALU 0 Data memory (integer and FP loads) 1 FP add 3 FP multiply 7 A) Assume that the results are fully bypassed. Using the standard single issue MIPS pipeline show the number of stall cycles for each instruction and what clock cycle each instruction begins execution (i.e., enters its first EX cycle) on the first iteration of the loop. How many clock cycles does each loop iteration take? B) Unroll the loop to make four copies of the body and schedule it for the standard MIPS pipeline. Re-order the instructions in order to maximize performance. How many clock cycles does each loop iteration take? C) Consider running the loop on a CDC scoreboard. What would be the state of scoreboard when the SLTIU instruction reaches the write result stage in the first iteration? Assume that issue and read operands stages each take one cycle. Assume that there are one integer functional unit, one FP multiplier, and one FP adder.
