辅导案例-L11 1

  • August 20, 2020

EEE225/NJP/L11 1 System I/O • Memory Mapped Peripherals • I2C Bus • Bus Contention EEE225/NJP/L11 2 Memory-mapped I/O Structure CPU Memory I/O Interface I/O Interface I/O Device I/O Device I/O Address I/O Data I/O Control Specialised data and control lines EEE225/NJP/L11 I/O Controller Interface 3 • Provides a consistent interface to the processor • Status registers indicate the state of the device • Processor can examine the status register to check on the transfer or device can interrupt the processor when ready • Data registers are used for the transfer of data EEE225/NJP/L11 4 Destination Initiated Transfer VALID DATAData Data Request ta th 1. Destination sends ‘Data Request’ control signal 2. After some delay, the source presents valid data 3. The destination reads the data – here, on the falling edge of Data Request 4. The source removes the data Timing Constraints • A data access time, ta • A minimum data hold time, th Asynchronous Data Transfer EEE225/NJP/L11 5 Source Initiated Transfer VALID DATAData Data Ready tsu th 1. Source outputs valid data 2. After some delay, the source asserts a ‘Data Ready’ control signal 3. The destination reads the data – here, on the rising edge of Data Ready 4. The source de-asserts Data Ready 5. Source removes valid data  Timing Constraints • A minimum data setup time, tsu • A minimum hold time, th EEE225/NJP/L11 6 The two previous transfers are known as strobing and will work as long as the responses of both the source and destination are predictable. (i.e. deterministic) If the response time is unpredictable, there is no way of knowing whether the data transfer has been completed properly. To ensure proper operation a technique known as handshaking is used. A second control signal is added from the end that did not initiate the transfer. Handshaking EEE225/NJP/L11 7 Source Initiated Transfer with Handshaking VALID DATAData Data Ready Data Acknowledge 1. Source asserts Data Ready and presents valid data 2. Destination reads the data (perhaps on the rising edge of Data Acknowledge) and asserts Data Acknowledge 3. Source removes data EEE225/NJP/L11 8 Destination Initiated Transfer with Handshaking VALID DATAData Data Request Data Valid 1. Destination asserts Data Request 2. Source responds with valid data 3. Source asserts Data Valid to say it has successfully produced the data 4. The destination reads the data, perhaps on the rising edge of Data Valid 5. Source removes data EEE225/NJP/L11 9 Inter-Integrated Circuit (I2C) Bus A simple two wire interface to connect peripherals. The I2C bus is a standard bidirectional interface that uses a controller, known as the master, to communicate with slave devices. © Texas Instruments EEE225/NJP/L11 10 A slave may not transmit data unless it has been addressed by the master. Each device on the I2C bus has a specific device address to differentiate between other devices that are on the same I2C bus. The physical I2C interface consists of the serial clock (SCL) and serial data (SDA) lines. Both SDA and SCL lines must be connected to VCC through a pull-up resistor. Data transfer may be initiated only when the bus is idle. A bus is considered idle if both SDA and SCL lines are high after a STOP condition. General I2C Operation © Texas Instruments EEE225/NJP/L11 11 Pulling the bus low Releasing the bus © Texas Instruments EEE225/NJP/L11 12 1. Suppose a master wants to send data to a slave: • Master-transmitter sends a START condition and addresses the slave- receiver • Master-transmitter sends data to slave-receiver • Master-transmitter terminates the transfer with a STOP condition 2. If a master wants to receive/read data from a slave: • Master-receiver sends a START condition and addresses the slave- transmitter • Master-receiver sends the requested register to read to slave-transmitter • Master-receiver receives data from the slave-transmitter • Master-receiver terminates the transfer with a STOP condition The general procedure for a master to access a slave device is the following: © Texas Instruments EEE225/NJP/L11 13 © Texas Instruments I2C communication with this device is initiated by the master sending a START condition and terminated by the master sending a STOP condition. A high-to-low transition on the SDA line while the SCL is high defines a START condition. A low-to- high transition on the SDA line while the SCL is high defines a STOP condition. START and STOP Conditions EEE225/NJP/L11 14 Single Byte Data Transfer One data bit is transferred during each clock pulse of the SCL. One byte is comprised of eight bits on the SDA line. A byte may either be a device address, register address, or data written to or read from a slave. Data is transferred Most Significant Bit (MSB) first. Any number of data bytes can be transferred from the master to slave between the START and STOP conditions. Data on the SDA line must remain stable during the high phase of the clock period, as changes in the data line when the SCL is high are interpreted as control commands (START or STOP). © Texas Instruments EEE225/NJP/L11 15 I2C Write to Slave Device’s Register To write on the I2C bus, the master will send a start condition on the bus with the slave’s address, as well as the last bit (the R/W bit) set to 0, which signifies a write. After the slave sends the acknowledge bit, the master will then send the register address of the register it wishes to write to. The slave will acknowledge again, letting the master know it is ready. After this, the master will start sending the register data to the slave, until the master has sent all the data it needs to (sometimes this is only a single byte), and the master will terminate the transmission with a STOP condition. © Texas Instruments EEE225/NJP/L11 16 Bus Contention © Texas Instruments Support Forum If one output is driving HIGH and the other LOW, there is bus contention and one of the devices may be damaged. For a 5V supply: Iout = 5/(25 + 25) = 100mA

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